1. Field of the Invention
The present invention relates to a data processing system, and more particularly to a data processing system having one or more processor modules.
2. Description of the Related Art
Data processing systems having a plurality of processor modules, each containing a central processing unit (CPU) and other electronic devices, can be broadly =divided into two types in terms of their memory configurations. One is called "symmetric systems," in which a plurality of processor modules are configured to exchange information via a common shared memory; the other is called "asymmetric systems," in which individual processing modules have their own memories. The former type (i.e., symmetric systems) is currently the mainstream architecture.
In symmetric data processing systems, processor modules are connected to a single, time-sharing memory bus, which is shared by two or more processor modules, but can be used by one processor at a time, microscopically. Each processor is allowed to occupy the bus for a limited time period, which can be a bottleneck in the scalability of the system. That is, with this conventional symmetric architecture, the system's total performance would not increase in proportion to the number of processor modules, because of the limitation in its shared bus access.
Bus arbitration mechanisms play an inevitable role in the symmetric data processing systems to arbitrate concurrent requests from two or more processor modules and appropriately allocate bus resources to them. The number of processor modules, on the other hand, may change in accordance with the system's cost and performance requirements. It is preferable that the system can be flexibly reconfigured by adding or removing optional processor modules. In the extreme case, such a system can even operate with only one processor module. The abovedescribed conventional bus arbitration mechanism still works as usual in such a single module system. However, bus arbitration is not necessary in this particular situation; rather, it causes an adverse effect to the system performance because it adds a delay to each cycle of shared memory access.